The present invention relates generally to the packaging of semiconductor devices and, more particularly, to interconnecting integrated circuits (ICs) on a substrate.
Electronic systems typically are manufactured from two or more ICs to provide complete system function. Until recently the limitations on performance and the number of I/O pins were not significant to the vast majority of applications. As more devices are integrated in a single IC and as clock speeds increase, however, limitations on performance and the number of I/O pins would be of paramount concern to semiconductor manufacturers. This is because the overall performance of an electronic system based on multiple ICs is a function of the performance of the individual ICs and of the performance of the signals between the ICs. The performance of the signals between the ICs is in turn a function of the number of signals and the electrical characteristics of the mechanism used to connect the I/O pins of the ICs. A more efficient mechanism for interconnecting ICs is therefore becoming an important influence on the cost, size, performance, weight, and efficiency of electronic systems.
Currently, the most common method used for interconnecting ICs is to first package the individual ICs, and then mount the packaged ICs on a substrate such as a printed circuit board. The size of the package is typically several times larger than the IC and is often manufactured from a metal bead frame and protected within a plastic molded case. The packaged ICs are then placed and soldered to a printed circuit board to create a complete electronic system. The advantages of that method include low cost and protection of the ICs during subsequent handling. In addition, the package acts as a standardized carrier for testing of the ICs, such that design changes to the printed circuit board may be made cheaply and quickly. Assembly of the IC to the printed circuit board may further be automated. Finally, such a system allows rework of the printed circuit.
A more efficient method is necessary, however, as advanced ICs require higher performance and a larger number of I/O pins than is possible with conventional interconnect technology. The conventional method has limited electrical performance and limited ability to remove heat. The electrical parasitic characteristics of the package, the length of the conductors, the electrical parasitic capacitance and inductance introduced by the structures of the printed circuit board, and the dielectric material properties used in the printed circuit board all limit the electrical performance of the method. These limitations in turn limit the number of signals on the system to at most a few hundred regardless of the complexity of the IC or the system. Since the current mechanism for IC interconnection has lower performance than the ICs, it limits the overall system performance. Integrated circuits are performing at above 1000 MHz. The current method of interconnecting ICs, however, is limited to systems operating well below 100 MHz.
As an example, current memory devices are limited by I/O constraints of low cost packaging and routing and cost constraints of the next level interconnect, typically glass laminate printed circuit boards. Memory capacity has increased by about 4 times every 3 years such that 256 Mbit (256xc3x971024xc3x971024) is available today, and 1 Gb will likely be available within the next two years. Meanwhile, the data width of memory devices has slowly increased from 1 MHz in the late 1970""s to 66 MHz two decades later or about 2 times every 5-6 years. The result is an increase in the time required to xe2x80x9cfillxe2x80x9d a DRAM or a drop in fill frequency and a limit on the available bandwidth. A semiconductor device can have hundreds of I/O but hundreds of I/O cannot be pinned out in a high volume low cost device such as a DRAM.
The present invention provides a system and a method for efficiently interconnecting a plurality of ICs to improve the electrical performance of the overall system. This is accomplished by providing high speed, high density, system level interconnect, including interchip routing lines, on the ICs, thereby reducing the routing complexity of the substrate or board on which the ICs are mounted. The technique can be used, for instance, to greatly increase the I/O for a memory component cost effectively such that the fill frequency is dramatically higher (e.g., 10 times or more).
In accordance with an aspect of the present invention, an integrated circuit device comprises an integrated circuit region including integrated circuit elements. An interconnect layer includes an insulative material, a plurality of conductive traces, and a plurality of conductive bond pads arranged in first and second subsets. A first subgroup of the conductive traces are connected to the integrated circuit elements in the integrated circuit region and are connected to the first subset of conductive bond pads. A second subgroup of the conductive traces are electrically insulated from the integrated circuit elements and are electrically insulated from the first subgroup of the conductive traces to form a pass through. The second subgroup of the conductive traces are connected to the second subset of conductive bond pads.
In accordance with another aspect of the invention, an integrated circuit structure comprises an insulative substrate having a plurality of signal traces and a plurality of bond sites disposed thereon. A subgroup of the plurality of signal traces are associated with a subset the plurality of bond sites with each of the signal traces in the subgroup extending from one of the plurality of bond sites in the subset. An integrated circuit device comprises an integrated circuit region including integrated circuit elements, and an interconnect layer. The interconnect layer includes an insulative material, a plurality of conductive traces, and a plurality of conductive bond pads arranged in first and second subsets. A first subgroup of the conductive traces are connected to the integrated circuit elements in the integrated circuit region and are connected to the first subset of conductive bond pads. A second subgroup of the conductive traces are electrically insulated from the integrated circuit elements and are electrically insulated from the first subgroup of the conductive traces to form a pass through. The second subgroup of the conductive traces are connected to the second subset of conductive bond pads. Each of the conductive bond pads of the integrated circuit device is connected with one of the bond sites in the subset.
In accordance with another aspect of the invention, an integrated circuit device comprises an integrated circuit region including integrated circuit elements. A passivation layer is formed on the integrated circuit region. An interconnect layer is formed on the passivation layer. The interconnect layer includes an insulative material, a plurality of conductive traces, and a plurality of conductive bond pads arranged in first and second subsets. A first subgroup of the conductive traces are connected to the integrated circuit elements in the integrated circuit region and are connected to the first subset of conductive bond pads. A second subgroup of the conductive traces are electrically insulated from the integrated circuit elements and are electrically insulated from the first subgroup of the conductive traces to form a pass through. The second subgroup of the conductive traces are connected to the second subset of conductive bond pads.